1. Field of Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, a semiconductor integrated circuit having a RAM built therein, such as, for example, a single chip microcomputer.
2. Description of Related Art
Typically, a RAM built in a semiconductor integrated circuit such as a single chip microcomputer transfers and receives signals to and from a central processing unit through a data bus. In other words, as shown in FIG. 2, for example, a RAM has columns or rows of memory cells defining memory cell columns ML1, ML2 . . . MLn that are connected to a data bus DB through input/output control circuits 2 provided for the respective memory cell columns ML1, ML2 . . . MLn. An input/output control circuit 2 is formed from two three-state circuits for writing and reading operations that are connected to one another in mutually inverse directions.
The data bus DB connects to the central processing unit (not shown). Each of the input/output control circuits 2 operates according to a logical sum of a writing command signal WR or a reading command signal RD and an enable signal CE1, CE2, . . . CEn provided from the central processing unit. The central processing unit controls the enable signals CE1, CE2 . . . CEn, and switches the enable signals CE1, CE2, . . . CEn set at an xe2x80x9cHxe2x80x9d level depending on the memory regions to be accessed. When the writing command signal WR is at an xe2x80x9cHxe2x80x9d level, those of the memory cell columns with the enable signal being at the xe2x80x9cHxe2x80x9d level become effective, and data from the central processing unit are transferred through the data bus DB and the input/output control circuits 2 and written in designated memory cells in the effective memory cell columns ML1, ML2 . . . MLn. Similarly, when the reading command signal RD is at an xe2x80x9cHxe2x80x9d level, those of the memory cell columns with the enable signal being at the xe2x80x9cHxe2x80x9d level become effective, and data stored in designated memory cells are transferred through those of the input/output control circuits 2 corresponding to the effective memory cell columns, and through the data bus DB to the central processing unit.
When the RAM is tested, test data is transferred from the central processing unit through the data bus DB and written in specified addresses in the RAM. Then, for the test of the RAM, the data stored in the specified addresses are read out onto the data bus DB and compared with the test data that is written, to thereby observe the status of the stored data that is read out.
Since the RAM is accessed through the central processing unit and the data bus DB, the number of the memory cells in which data can be simultaneously written is limited. Similarly, when stored data is read from the memory cell columns ML1, ML2, . . . MLn, the number of data that can be simultaneously read out is limited.
Although the number of data that can be simultaneously written or read is limited, the user may not feel that the processing time required for such operations is very long. The processing time required for writing or reading data is relatively short compared with the operation time that is spent by the user, and therefore does not make the user feel inconvenient and does not present any problems to the user. However, when operation tests are conducted on semiconductor integrated circuits before shipping, test data are written in all addresses in each of the semiconductor integrated circuits, and then the stored data is read from all of the addresses. Accordingly, the processing time for writing or reading the data is relatively long with respect to the overall test time. In other words, the fact that the number of data that can be simultaneously written or read is limited poses a major obstacle to an effort in shortening the test time.
To avoid such an obstacle, a RAM may be divided into a plurality of blocks. Test data can be simultaneously written in a plurality of addresses. However, when data stored in the RAM is read, the read data may collide with one another on the data bus. Therefore, it is difficult to simultaneously read the stored data.
Therefore, the present invention has been made at least in view of the unsolved problems of the conventional technique, and an object of the present invention is to provide a semiconductor integrated circuit that can readily perform a test on RAMs mounted therein.
A semiconductor integrated circuit according to an exemplary embodiment of the present invention, in which data stored in a storage region is read through a data bus, may consist of a first reading device that is interposed between the storage region and the data bus and that reads out data stored in the storage region, a second reading device that reads out data stored in the storage region independently of the first reading device and that outputs to an individual output terminal provided for the respective stored data, and a switching device that switches in response to a mode-switching signal between reading of the stored data by the first reading device and reading of the stored data by the second reading device.
According to this exemplary embodiment of the present invention, the first reading device is provided between the storage region and the data bus, and stored data is read by the first reading device from the storage region onto the data bus. Furthermore, the second reading device reads out data stored in the storage region independently of the first reading device and outputs the data to each of the individual output terminals provided for the respective stored data. Also, the switching device switches in response to a mode-switching signal between reading of the stored data by the first reading device and reading of the stored data by the second reading device.
In other words, the stored data read out by the second reading device is outputted to each of the individual output terminals provided for the respective stored data. Therefore, for example, the stored data may be read out in the unit of the number of the output terminals. As a result, the stored data can be retrieved in the unit of the number of the output terminals without the plural stored data being collided.
It is noted that, when the stored data is read through the data bus, the number of the data that can be read is limited due to the bit number of the data bus or the like. This does not pose any problems in the normal use of the semiconductor integrated circuit. However, when an operation test is conducted on the semiconductor integrated circuit, test data is written in the storage region, and then the stored data is read from the storage region to observe the stored data. Therefore, it takes a long time for reading the stored data alone.
In this case, the switching device switches from an operation of reading the stored data through the data bus by the first reading device to an operation of reading the stored data by the second reading device, such that a plurality of stored data are read out to the output terminals. As a result, the stored data can be read in the unit of the number of the output terminals, and thus the time required for reading out the stored data can be shortened.
Also, in accordance with another exemplary embodiment, the semiconductor integrated circuit may further consist of an output terminal for outputting a signal that is different from the stored data read out by the second reading device, wherein the output terminal is commonly used for outputting the stored data read out by the second reading device.
In accordance with the present invention set forth this exemplary embodiment, an output terminal provided for outputting a signal that is different from the stored data read out by the second reading device is commonly used for outputting the stored data read out by the second reading device. Accordingly, an independent output terminal does not need to be provided for outputting stored data read by the second reading device.
In another exemplary embodiment in the semiconductor integrated circuit, the second reading device is structured in a manner that a plurality of stored data can be simultaneously read out.
In accordance with the present invention set forth in this exemplary embodiment, the second reading device simultaneously reads a plurality of stored data, and outputs the stored data to the individual output terminals. Accordingly, a plurality of stored data can be simultaneously retrieved from the output terminals.
For example, when memory cells are disposed in a matrix to form a storage region, and the first reading device reads and writes data in and from each of memory cell columns in the matrix, stored data is read from the memory cells one by one in each of the memory cell columns, and is outputted to each of the respective individual output terminals. As a result, the stored data can be read out in the unit of the number of the memory cell columns.
In another exemplary embodiment, in the semiconductor integrated circuit, the second reading device successively outputs a plurality of stored data to a common output terminal at different timings.
In accordance with the present invention set forth in this exemplary embodiment, a plurality of stored data are outputted to a common output terminal, and the plurality of the stored data are successively outputted at different timings. Therefore, even when the number of the output terminals that can be commonly used is smaller than the number of the stored data to be retrieved from the output terminals, the stored data can be successively outputted to the common output terminal at different timings, i.e., at timings that allow retrieving the stored data from the common output terminal. As a result, a plurality of the stored data can be retrieved without the data being collided with one another.
A semiconductor integrated circuit according to another exemplary embodiment of the present invention, in which data stored in a storage region is read through a data bus, may consist of a plurality of writing devices that are capable of writing data via the data bus in specified regions of the storage region, and a write control device that operates any one of the writing devices and switches the writing devices to be operated from one to the other to thereby control writing data in the storage region, wherein the write control device operates the plurality of the writing devices to simultaneously perform writing operations in a test mode.
In accordance with the present invention set forth in this exemplary embodiment, the plurality of writing devices capable of writing data via the data bus in specified regions of the storage region are provided between the storage region and the data bus. The write control device controls the writing devices, and successively switches the writing devices to be operated from one to the other, such that data provided through the data but are written in specified regions of the storage region through the writing devices that are operated by the write control device. The writing devices are switched from one to the other, such that the data are successively written in specified regions of the storage region.
In a test mode, the write control device operates the plurality of writing devices to simultaneously write data in a plurality of regions. Accordingly, for example, when test data is written in various areas of the storage region to conduct an operation test on the semiconductor integrated circuit, the writing devices are switched to the test mode in which the writing devices simultaneously operate, such that the test data from the data bus are written in the specified areas of the storage region through the respective corresponding writing devices. Accordingly, data can be written in the storage area in the unit of the number of the writing devices, and therefore the time required for writing test data can be shortened.